EPM5128JC vs EPM5128GM883B Vergleich
Detaillierter Direktvergleich von EPM5128JC von Altera und EPM5128GM883B von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5128JC | EPM5128GM883B |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,75 | $159,25 |
| Product Family | MAX 5000 | — |
| Device Type | EPLD / CPLD | UV EPLD (Erasable Programmable Logic Device) |
| Macrocell Count | 128 | — |
| Propagation Delay (tPD) | 35 ns | — |
| Logic Elements | Programmable AND/OR/XOR array | — |
| Supply Voltage (VCC) | 5 V (typical) | — |
| Anzahl der Pins | 68 | — |
| Package Type | PLCC-68 (JLCC) ceramic, J-leaded | — |
| Dedicated Inputs | 8 | 7 |
| User I/O Pins | [DATA_NEEDED: user I/O pin count] | 52 |
| Configuration Memory | UV-erasable EPROM (windowed package) | UV-erasable EPROM |
| Programming Interface | Altera MAX+PLUS II / A+PLUS / legacy programmer | — |
| Betriebstemperatur | Commercial 0C to +70C | -55C to +125C (military) |
| Montageart | Surface Mount (PLCC socket or solder) | — |
| Boundary Scan | JTAG IEEE 1149.1 (family feature) | — |
| Process Technology | CMOS EPROM | — |
| RoHS-Status | [DATA_NEEDED: RoHS status - legacy part] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Family | — | MAX 5000 |
| Macrocells | — | 128 |
| Logic Array Blocks (LABs) | — | 8 |
| Propagation Delay (tpd) | — | 55 ns |
| External Clock Inputs | — | 1 |
| Technology | — | CMOS |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Gehäuse | — | PGA-883 (ceramic pin grid array) |
| Qualification | — | MIL-STD-883 Class B (suffix 883B) |
| Program/Erase Method | — | UV-erasable |