EPM5128JI-2 vs EPM5130JI Vergleich
Detaillierter Direktvergleich von EPM5128JI-2 von Altera und EPM5130JI von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5128JI-2 | EPM5130JI |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $16,40 | $9,75 |
| Device Type | UV-Erasable Programmable Logic Device (PLD) | UV-Erasable EPLD (CMOS EPROM) |
| Series | MAX 5000 | — |
| Macrocells | 128 | 128 |
| Dedicated Inputs | 7 | — |
| User I/O Pins | 52 | — |
| Propagation Delay (tPD) | 45 ns | 55 ns |
| Maximale Taktfrequenz | 50 MHz | 33.3 MHz |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | — |
| Betriebstemperatur | -40 C to +85 C (industrial) | Commercial (0C to +70C) |
| Package Type | Ceramic J-Lead (JI) with UV window | Ceramic J-Leaded Chip Carrier (JLCC) with UV window |
| Process Technology | CMOS EPROM | 0.75 micron CMOS EPROM |
| Programmability | UV-erase, parallel programmer | — |
| Architecture | LAB-based macrocell, segmented interconnect | — |
| Speed Grade | -2 (industrial-speed) | — |
| RoHS-Status | unknown | Non-compliant (contains Pb in ceramic package) |
| Lead-Free | unknown | — |
| Family | — | MAX 5000 |
| Logic Array Blocks (LABs) | — | 8 |
| External Clock Inputs | — | 1 (shared input/clock) |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Versorgungsspannung | — | 5 V (typical) |
| Input Logic Standard | — | TTL-compatible |
| Program/Erase Method | — | UV erasure through quartz window |
| Lifecycle | — | Obsolete - EOL by Altera/Intel |