EPM5130JI vs EPM5130GI Vergleich
Detaillierter Direktvergleich von EPM5130JI von Altera und EPM5130GI von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5130JI | EPM5130GI |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,75 | $16,20 |
| Family | MAX 5000 | — |
| Device Type | UV-Erasable EPLD (CMOS EPROM) | — |
| Macrocells | 128 | 128 |
| Logic Array Blocks (LABs) | 8 | 8 |
| Maximale Taktfrequenz | 33.3 MHz | — |
| Propagation Delay (tPD) | 55 ns | 55 ns |
| External Clock Inputs | 1 (shared input/clock) | — |
| Interconnect | Programmable Interconnect Array (PIA) | Programmable Interconnect Array (PIA) |
| Process Technology | 0.75 micron CMOS EPROM | CMOS |
| Versorgungsspannung | 5 V (typical) | 5 V |
| Input Logic Standard | TTL-compatible | — |
| Package Type | Ceramic J-Leaded Chip Carrier (JLCC) with UV window | — |
| Betriebstemperatur | Commercial (0C to +70C) | -40C to +85C (industrial) |
| Program/Erase Method | UV erasure through quartz window | — |
| RoHS-Status | Non-compliant (contains Pb in ceramic package) | [DATA_NEEDED: RoHS status] |
| Lifecycle | Obsolete - EOL by Altera/Intel | — |
| Device Family | — | MAX 5000 |
| Architecture | — | EPLD (Erasable Programmable Logic Device), UV-erasable |
| Dedicated Inputs | — | 19 |
| Total Inputs | — | 68 |
| I/O Pins | — | 48 |
| Maximum Clock Frequency (fMAX) | — | 33.3 MHz |
| External Clock Pins | — | 1 |
| Gehäuse | — | Ceramic Pin Grid Array (PGA), windowed |
| Programming Method | — | UV erasure + EPROM programming |