EPM5130LC vs EPM5192-1LC Vergleich
Detaillierter Direktvergleich von EPM5130LC von Altera und EPM5192-1LC von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5130LC | EPM5192-1LC |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $15,60 | $19,40 |
| Series | MAX 5000 | — |
| Family | MAX 5000 (EPM51xx) | MAX 5000 |
| Macrocells | 128 | 192 |
| Logic Array Blocks (LABs) | 8 | 4 |
| User I/O Pins | 48 | 64 |
| Total Inputs (Dedicated + I/O) | 68 | — |
| Dedicated Inputs | 19 | — |
| Propagation Delay (tPD) | 55 ns | — |
| Maximum Internal Clock Frequency | 50 MHz | — |
| Global Clock Inputs | 1 | — |
| Configuration Technology | UV-Erasable / OTP EPROM | — |
| Process Technology | CMOS (0.7 um EPROM) | UV EPROM, erasable windowless |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | — |
| I/O Standard | TTL-compatible | — |
| Gehäuse | JLCC-68 (J-Lead Ceramic Chip Carrier) | 64-pin Ceramic J-Lead Chip Carrier (LC) |
| Betriebstemperatur | [DATA_NEEDED: commercial/industrial/military grade] | 0C to +70C (commercial) |
| Montageart | Surface Mount | Surface Mount |
| RoHS-Status | Non-compliant (ceramic JLCC, contains lead) | Non-compliant (ceramic windowless package, lead-bearing termination) |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 3,750 |
| Maximum Operating Frequency | — | 62.5 MHz |
| Propagation Delay (tpd) | — | [DATA_NEEDED: -1 speed grade tpd in ns] |
| Versorgungsspannung | — | 5 V |
| Programmable Interconnect | — | PIA (Programmable Interconnect Array) |
| JTAG Boundary Scan | — | IEEE 1149.1 compliant |