EPM5130WM883B-1 vs EPM5130WC-1 Vergleich
Detaillierter Direktvergleich von EPM5130WM883B-1 von Altera und EPM5130WC-1 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM5130WM883B-1 - 128-Macrocell UV PLD, 5V, CQFP-100 | Altera MAX 5000
EPM5130WM883B-1 ObsoleteIntel
EPM5130WC-1 - 128-Macrocell 40ns UV CPLD, 100-pin CQFP | Intel (Altera) MAX 5000
EPM5130WC-1 ObsoleteSpezifikationsvergleich
| Parameter | EPM5130WM883B-1 | EPM5130WC-1 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $128,00 | $85,00 |
| Device Family | MAX 5000 (Classic EPLD) | — |
| Manufacturer | Altera (now Intel PSG) | Altera (now Intel) |
| Logic Type | UV-Erasable Programmable Logic Device (EPLD) | — |
| Technology | CMOS, EPROM cell | — |
| Macrocells | 128 | — |
| Logic Array Blocks (LABs) | 8 | — |
| Dedicated Inputs | 19 | — |
| I/O Pins | 48 (bi-directional) | — |
| Propagation Delay (tPD) | 55 ns | — |
| Maximum Clock Frequency (fMAX) | 33.3 MHz | — |
| Supply Voltage (VCC) | 4.5 V to 5.5 V (nominal 5 V) | — |
| External Clock Inputs | 1 global + shared inputs | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Package Type | CQFP-100, ceramic windowed (WM) | 100-pin Ceramic QFP (Windowed) |
| Military Screening | MIL-STD-883 Class B (883B suffix) | — |
| Betriebstemperatur | [DATA_NEEDED: military/industrial temperature grade] | [DATA_NEEDED: operating temperature range] |
| Programming Method | UV erase + EPROM programming | — |
| RoHS-Status | [DATA_NEEDED: confirmed RoHS for ceramic windowed CQFP] | [DATA_NEEDED: RoHS compliance] |
| Montageart | Surface Mount (CQFP with J-leads) | Surface Mount |
| Series | — | MAX 5000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocell Count | — | 128 |
| Logic Array Blocks | — | Multiple LABs (per MAX 5000 architecture) |
| Propagation Delay (tpd) | — | 40 ns |
| Maximale Taktfrequenz | — | 50 MHz |
| Erasure Method | — | UV (ultraviolet, windowed package) |
| Process Technology | — | CMOS EPROM |
| User I/O Pins | — | Up to 100 |
| Versorgungsspannung | — | [DATA_NEEDED: VCC nominal] |
| Programmable | — | Yes (UV-erasable, non-volatile) |
| Logic Family | — | MAX 5000 (Altera) |
| Configuration Memory | — | EPROM (on-chip) |