EPM5192-1LC vs EPM5192LC-1 Vergleich
Detaillierter Direktvergleich von EPM5192-1LC von Altera und EPM5192LC-1 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5192-1LC | EPM5192LC-1 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $19,40 | $14,20 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | CPLD (Complex Programmable Logic Device) | EPLD / CPLD |
| Usable Gates | 3,750 | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 4 | — |
| User I/O Pins | 64 | — |
| Maximum Operating Frequency | 62.5 MHz | — |
| Propagation Delay (tpd) | [DATA_NEEDED: -1 speed grade tpd in ns] | — |
| Versorgungsspannung | 5 V | 5 V nominal (4.75 V to 5.25 V) |
| Process Technology | UV EPROM, erasable windowless | — |
| Programmable Interconnect | PIA (Programmable Interconnect Array) | — |
| JTAG Boundary Scan | IEEE 1149.1 compliant | — |
| Gehäuse | 64-pin Ceramic J-Lead Chip Carrier (LC) | — |
| Montageart | Surface Mount | — |
| Betriebstemperatur | 0C to +70C (commercial) | 0C to +70C (commercial) |
| RoHS-Status | Non-compliant (ceramic windowless package, lead-bearing termination) | Non-compliant (ceramic LDCC with Pb-bearing terminations) |
| Logic Gates | — | 3750 (typical usable) |
| Dedicated Inputs | — | 7 |
| User I/O | — | 64 |
| Anzahl der Pins | — | 84 |
| Package Type | — | LDCC (Leaded Ceramic Chip Carrier), plastic windowless |
| Propagation Delay | — | 25 ns |
| Maximale Taktfrequenz | — | 50 MHz |
| Technology | — | CMOS, UV-erasable / OTP EPROM cell |
| Programmable Memory | — | EPROM (one-time or UV-erasable) |
| Speed Grade | — | -1 |