EPM5192AJI84-15 vs EPM5192AGC84-20 Vergleich

Detaillierter Direktvergleich von EPM5192AJI84-15 von Altera und EPM5192AGC84-20 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5192AJI84-15 EPM5192AGC84-20
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $27,80 $41,20
Device Family MAX 5000 EPLD —
Product Type UV-Erasable / OTP Complex PLD Complex Programmable Logic Device (CPLD)
Macrocells 192 192
Logic Array Blocks (LABs) 16 —
User I/O Pins 84 64
Propagation Delay (tPD) 15 ns —
Supply Voltage (VCC) 4.5 V to 5.5 V (nominal 5 V) —
Process Technology CMOS EPROM (UV-erasable) CMOS
Package Type 84-pin JLCC (J-Leaded Ceramic Chip Carrier) with quartz window —
Montageart Through-Hole (SMD socket-compatible) Through-Hole (Pin Grid Array socket)
Betriebstemperatur -40 °C to +85 °C (Industrial, 'I' suffix) —
Programming Method UV erase + EPROM program via standard Altera programmer —
Design Tool Support MAX+PLUS II (legacy); not supported by modern Quartus Prime —
RoHS-Status unknown [DATA_NEEDED: RoHS compliance]
Lead-Free unknown —
Halogenfrei unknown —
Functional Equivalent (Plastic OTP) EPM5192AJC84-15 (windowless plastic JLCC, same die) —
Family — MAX 5000
Dedicated Inputs — 7
Logic Gates (typical) — [DATA_NEEDED: typical gate count]
Maximum Clock Frequency (fMAX) — 66.7 MHz
Pin-to-Pin Delay (tPD) — 20 ns
Speed Grade — -20
Gehäuse — 84-pin Ceramic Pin Grid Array (CPGA, WPGA)
Package Code — WPGA
Erasure Method — UV-Erasable (with OTP window)
Operating Temperature Grade — Commercial
Versorgungsspannung — [DATA_NEEDED: VCC range]
I/O Standard — 5V CMOS / TTL compatible

Datenblätter & Ressourcen

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