EPM5192ALI84-20 vs EPM5192ALC84-20 Vergleich

Detaillierter Direktvergleich von EPM5192ALI84-20 von Altera und EPM5192ALC84-20 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5192ALI84-20 EPM5192ALC84-20
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $9,90 $19,40
Family MAX 5000 —
Device Type EPLD (UV-erasable / OTP Complex PLD) UV-Erasable/OTP Complex PLD (EPLD)
Macrocells 192 192
Process Technology CMOS, EPROM-based CMOS
Propagation Delay (tPD) 20 ns (pin-compatible speed grade) —
User I/O Pins (max) 84 (in PLCC-84 package) —
Versorgungsspannung 5 V (single supply, TTL-compatible I/O) —
Operating Temperature Grade Industrial (I) —
Package Code QCCJ (Plastic Leaded Chip Carrier, J-bend) QCCJ (PLCC-84)
Package Type PLCC-84 (PQCC-84) —
No. of Terminals 84 —
Form of Terminal J-BEND —
Montageart Surface Mount (PLCC socket compatible) Surface Mount (PLCC socket-compatible)
Programmability UV-erasable / one-time programmable (OTP) —
Logic Type Combinatorial and registered, per-macrocell DFF —
I/O Standard TTL-compatible —
RoHS-Status [DATA_NEEDED: RoHS status - Altera MAX 5000 series is generally legacy and may not be RoHS compliant] [DATA_NEEDED: RoHS status not in provided web data]
Series — Altera MAX 5000
Speed Grade — -20 (20 ns pin-to-pin delay)
Gehäuse — 84-pin PLCC (Plastic Leaded Chip Carrier)
Terminal Pitch — 1.270 mm
Terminal Form — J-bend
Package Shape — Square
Temperature Grade — Commercial
Programming Method — UV-erase + EPROM (One-Time-Programmable option)
Logic Family — MAX 5000 EPLD
I/O Compatibility — TTL-compatible
Configuration Memory — EPROM (UV-erasable)

Datenblätter & Ressourcen

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