EPM5192AQC-2 vs EPM5192C-2 Vergleich
Detaillierter Direktvergleich von EPM5192AQC-2 von Altera und EPM5192C-2 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5192AQC-2 | EPM5192C-2 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $21,50 | $13,20 |
| Device Type | UV-Erasable / OTP Complex PLD (CPLD) | Complex Programmable Logic Device (CPLD) |
| Series | MAX 5000 (EPM5192) | — |
| Macrocells | 192 | 192 |
| User I/O Pins | 64 | 64 |
| Dedicated Inputs | 7 | 7 |
| Total Inputs | 72 | — |
| Propagation Delay (tPD) | 45 ns (-2 speed grade) | — |
| Maximale Taktfrequenz | [DATA_NEEDED: max fMAX for -2 grade] | — |
| Process Technology | CMOS | CMOS |
| Switch Matrix | UV-Erasable / OTP (windowless on AQC package) | — |
| Gehäuse | 100-pin PQFP (R-PQFP-G100) | — |
| Lead Pitch | 0.635 mm | — |
| Terminal Form | Gull-wing | — |
| Betriebstemperatur | [DATA_NEEDED: commercial / industrial / military grade] | — |
| Montageart | Surface Mount | — |
| Programming Interface | JTAG (IEEE 1149.1) boundary scan | JTAG / Altera MAX+ programming |
| RoHS-Status | [DATA_NEEDED: confirmed compliance status] | unknown |
| Family | — | MAX 5000 |
| Logic Array Blocks (LABs) | — | 12 |
| External Clock Inputs | — | 1 |
| Propagation Delay (PIA, typical) | — | 45 ns |
| Maximum Operating Frequency | — | 50 MHz |
| Configuration Memory | — | EEPROM (non-volatile) |
| Programmable Interconnect | — | Programmable Interconnect Array (PIA) |
| Speed Grade | — | -2 |
| Lead-Free | — | unknown |