EPM5192AQI100-20 vs EPM5192AQC100-20 Vergleich
Detaillierter Direktvergleich von EPM5192AQI100-20 von Altera und EPM5192AQC100-20 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM5192AQI100-20 - MAX 5000 192-Macrocell EPLD, 20ns, PQFP-100 | Altera
EPM5192AQI100-20 ObsoleteSpezifikationsvergleich
| Parameter | EPM5192AQI100-20 | EPM5192AQC100-20 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $18,90 | $11,85 |
| Family | MAX 5000 EPLD | — |
| Device Series | EPM5192 | — |
| Technology | CMOS, UV-erasable EPROM | — |
| Propagation Delay | 20 ns (speed grade -20) | — |
| Logic Array Blocks (LABs) | 12 | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Macrocell Count | 192 | — |
| Dedicated Inputs | 7 | — |
| I/O Pins | 64 bidirectional | — |
| Gehäuse | 100-pin PQFP (R-PQFP-G100) | 100-lead PQFP (R-PQFP-G100) |
| JEDEC Package Outline | R-PQFP-G100 | — |
| Betriebstemperatur | Industrial grade ("I" suffix) | — |
| Montageart | Surface Mount (PQFP) | Surface Mount (PQFP) |
| Architecture | Classic EPLD, deterministic timing | — |
| Design Tool | Altera MAX+PLUS II (legacy) | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Versorgungsspannung | [DATA_NEEDED: VCC range] | 5 V (typical, MAX 5000 family) |
| Device Family | — | MAX 5000 |
| Product Type | — | Complex Programmable Logic Device (CPLD) |
| Macrocells | — | 192 |
| Maximum Operating Frequency | — | 66.7 MHz |
| Propagation Delay (tpd) | — | 33 ns |
| Terminal Pitch | — | 0.65 mm |
| Process Technology | — | CMOS |
| Programming Technology | — | UV-Erasable / One-Time-Programmable (OTP) |
| Betriebstemperaturbereich | — | [DATA_NEEDED: operating temperature range] |
| I/O Count | — | [DATA_NEEDED: usable I/O count] |
| Logic Array Blocks | — | Multiple LABs (per MAX 5000 architecture) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| MSL-Level | — | [DATA_NEEDED: MSL rating] |