EPM5192GM883B-2 vs EPM5192JC-1N Vergleich
Detaillierter Direktvergleich von EPM5192GM883B-2 von Altera und EPM5192JC-1N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5192GM883B-2 | EPM5192JC-1N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $142,00 | $19,85 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | CPLD (Complex Programmable Logic Device), UV-erasable | CPLD - Complex Programmable Logic Device |
| Macrocells | 192 | 192 |
| Propagation Delay (tPD) | 45 ns (-2 speed grade) | 40 ns |
| Maximum Internal Clock Frequency | 33.3 MHz | — |
| Supply Voltage (VCC, nominal) | 5 V | — |
| Technology | 5 V CMOS | CMOS EPROM (UV-erasable) |
| Dedicated Inputs | 7 | 7 |
| User I/O Pins | 64 | 64 |
| Gehäuse | 84-pin Ceramic Pin Grid Array (CPGA), code S-CPGA-P84 | 84-pin Ceramic Quad Flat Pack (CQFP) |
| Package Outline | 28.45 mm square (approx.) | — |
| Military Screening | MIL-STD-883 (per '883' suffix) | — |
| Montageart | Through-hole PGA socket | — |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: industrial/commercial temperature range] |
| RoHS-Status | non_compliant (ceramic CPGA with MIL-STD-883 screening) | — |
| JEDEC Package Code | S-CPGA-P84 | S-CQCC-J84 |
| Logic Array Blocks (LABs) | — | 12 |
| Usable Gates | — | 3750 |
| External Clock Inputs (GCLK) | — | 1 |
| Maximum Clock Frequency (fMAX) | — | 62.5 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Programming Interface | — | JTAG / Altera ByteBlaster |