EPM5192JI vs EPM5192GC-1 Vergleich
Detaillierter Direktvergleich von EPM5192JI von Altera und EPM5192GC-1 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5192JI | EPM5192GC-1 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,75 | $17,85 |
| Family | MAX 5000 | MAX 5000 (Classic) |
| Device Type | EPLD (UV-erasable CMOS Programmable Logic Device) | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 |
| User I/O Pins | 64 | 64 |
| Dedicated Inputs | 7 | 7 |
| Propagation Delay (tpd) | 55 ns | — |
| Versorgungsspannung | 4.75 V to 5.25 V (nominal 5 V) | — |
| Technology | CMOS EPROM, UV-erasable | — |
| Gehäuse | 84-pin PLCC (windowed, J-suffix ceramic) | 100-pin Ceramic PGA (GC) |
| Betriebstemperatur | -40 C to +125 C (industrial, I-suffix) | [DATA_NEEDED: operating temperature grade] |
| Montageart | Surface Mount (PLCC socket recommended for UV erasure) | Through-Hole (PGA) |
| RoHS-Status | [DATA_NEEDED: RoHS status - pre-2010 part, likely non-compliant] | [DATA_NEEDED: RoHS status] |
| Programming Method | Altera MAX 5000 programming algorithm (device programmer) | — |
| Erasure Method | UV exposure through windowed package | — |
| Logic Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 3,750 |
| Maximum Propagation Delay (tPD) | — | 40 ns |
| Maximum Frequency (fMAX) | — | 62.5 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Process Technology | — | CMOS, UV-erasable / OTP |
| Configuration Method | — | UV-Erase / One-Time Programmable |
| Interconnect | — | Peripheral Interconnect Array (PIA) |