EPM5192LC vs EPM5192GC-1 Vergleich
Detaillierter Direktvergleich von EPM5192LC von Altera und EPM5192GC-1 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5192LC | EPM5192GC-1 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $28,40 | $17,85 |
| Family | MAX 7000S | MAX 5000 (Classic) |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 |
| User I/O Pins | 64 | 64 |
| Dedicated Inputs | 7 | 7 |
| Global Clock Inputs | 1 | — |
| Propagation Delay (tPD) | 55 ns (typical, commercial) | — |
| Maximum Clock Frequency (fMAX) | 50 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (nominal 5 V) | 4.75 V to 5.25 V |
| Process Technology | CMOS, UV-erasable/OTP EPROM configuration | CMOS, UV-erasable / OTP |
| Programmable Interconnect | Programmable Interconnect Array (PIA), fixed delay | — |
| Boundary-Scan Support | JTAG IEEE 1149.1 | — |
| Programming Interface | JTAG (ByteBlaster-compatible) | — |
| Operating Temperature (commercial) | 0C to +70C | — |
| Gehäuse | JLCC-68 (windowed ceramic, LC suffix) | 100-pin Ceramic PGA (GC) |
| Montageart | Surface Mount | Through-Hole (PGA) |
| RoHS-Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Logic Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 3,750 |
| Maximum Propagation Delay (tPD) | — | 40 ns |
| Maximum Frequency (fMAX) | — | 62.5 MHz |
| Configuration Method | — | UV-Erase / One-Time Programmable |
| Interconnect | — | Peripheral Interconnect Array (PIA) |
| Betriebstemperatur | — | [DATA_NEEDED: operating temperature grade] |