EPM5192LC84-2 vs EPM5192LI-2 Vergleich
Detaillierter Direktvergleich von EPM5192LC84-2 von Altera und EPM5192LI-2 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5192LC84-2 | EPM5192LI-2 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $7,10 | $7,90 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (UV-Erasable / OTP Complex PLD) | EPLD (Erasable/OTP Complex PLD) |
| Macrocells | 192 | 192 |
| Gehäuse | 84-pin PLCC (LC) | 84-pin PLCC (J-lead), JEDEC S-PQCC-J84 |
| Speed Grade | -2 | — |
| Versorgungsspannung | 5 V (TTL-compatible I/O) | 4.5 V to 5.5 V |
| Technology | CMOS, UV-erasable / OTP | CMOS, UV-erasable / OTP |
| Logic Elements | AND-OR array with macrocell flip-flops | — |
| Programming Method | Altera legacy programmer (JEDEC bitstream) | — |
| Betriebstemperatur | Commercial (0C to +70C) | -40 C to +85 C (industrial) |
| Montageart | Surface Mount | Surface Mount |
| RoHS-Status | Non-compliant (SnPb lead finish typical for this vintage) | [DATA_NEEDED: RoHS status] |
| Lebenszyklusstatus | Obsolete (last Altera MAX 5000 production) | — |
| JTAG Support | Vendor-specific programming interface (pre-IEEE 1532) | — |
| I/O Standard | TTL, 5V CMOS-compatible | — |
| Logic Array Blocks (LABs) | — | 12 |
| User I/O | — | 64 |
| Total Inputs | — | 72 (7 dedicated + 64 I/O) |
| Propagation Delay (tpd) | — | 55 ns (max) |
| Maximum Internal Frequency | — | 100 MHz |
| Typical Power Dissipation | — | 600 mW at 5 V / 25 C |
| Design Toolchain | — | Altera MAX+plus II |