EPM5192LI84 vs EPM5192LI-1 Vergleich

Detaillierter Direktvergleich von EPM5192LI84 von Altera und EPM5192LI-1 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5192LI84 EPM5192LI-1
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete NRND
Lagerstatus In Stock In Stock
Stückpreis (USD) $21,60 $16,40
Device Family MAX 5000 —
Product Type UV-Erasable/OTP Complex PLD (CPLD) —
Usable Gates 3,750 gates 3,750
Macro Cells 192 —
Maximum Toggle Frequency 40 MHz 40 MHz
Pin-to-Pin Delay (tPD) 25 ns —
Supply Voltage (VCC) 5 V (single supply) —
User I/O Pins 64 (max) [DATA_NEEDED: user I/O count for JLCC variant]
Betriebstemperaturbereich -40 °C to +85 °C (industrial) —
Package Type 84-pin PLCC (J-lead, package code J84/QCCJ) JLCC (windowed, ceramic, UV-erasable)
Montageart Surface Mount (socket-compatible) Surface Mount (JLCC with J-leads)
Configuration Memory OTP / UV-erasable EPROM —
Programming Method Stand-alone programmer (no JTAG on LI84 OTP variant) —
RoHS-Status [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status of ceramic LI variant]
Logic Compatibility TTL-compatible I/O —
Family — MAX 5000
Device Type — EPLD (UV-Erasable/OTP Complex PLD)
Macrocells — 192
Versorgungsspannung — 5 V
Propagation Delay (tPD) — [DATA_NEEDED: tPD in ns at -1 grade]
Process Technology — CMOS EPROM, UV-erasable
Speed Grade — -1
Betriebstemperatur — [DATA_NEEDED: industrial vs military range]
Pin-Anzahl — [DATA_NEEDED: pin count of LI package]
MSL-Level — [DATA_NEEDED: MSL level]
Lead Free — [DATA_NEEDED: lead-free]
Programmable Interconnect — Programmable Interconnect Array (PIA)
Architecture — EEPROM/EPROM-based, non-volatile, instant-on

Datenblätter & Ressourcen

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