EPM570F100A5N vs EPM570F100C5N Vergleich
Detaillierter Direktvergleich von EPM570F100A5N von Altera und EPM570F100C5N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM570F100A5N | EPM570F100C5N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,85 | $5,20 |
| Family | MAX II | MAX II |
| Logic Elements | 570 | 570 |
| Macrocells | 440 | — |
| User Flash Memory | 8 Kbits | — |
| Pin-to-Pin Delay (tPD) | 5.4 ns | — |
| Maximum Operating Frequency | 201.1 MHz | — |
| User I/O Pins (max) | 76 | — |
| Global Clock Lines | 4 | — |
| Supply Voltage - Core | 3.3 V | — |
| Supply Voltage - I/O Banks | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Process Technology | 0.18 µm flash | 0.18 micron CMOS |
| Gehäuse | 100-ball FBGA | — |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | JTAG (IEEE 1149.1) |
| Betriebstemperatur | 0°C to +85°C (commercial) | 0C to 85C (TJ) |
| RoHS-Status | Compliant | — |
| Number of Macrocells | — | 440 |
| User I/Os | — | 76 |
| Number of Logic Array Blocks | — | 57 |
| Propagation Delay (tPD) | — | 5.4 ns |
| Supply Voltage - Internal | — | 2.5 V, 3.3 V |
| I/O Standards Supported | — | 1.8 V, 2.5 V, 3.3 V LVCMOS/LVTTL |
| Montageart | — | Surface Mount |
| Gehäuse / Bauform | — | 100-LBGA (FBGA-100), 11 x 11 mm, 1.0 mm pitch |
| Supplier Device Package | — | 100-FBGA |
| Configuration Memory | — | On-chip Flash (instant-on, non-volatile) |
| In-System Programmability | — | Yes (JTAG, IEEE 1532) |
| User Flash Memory (UFM) | — | 8 Kbit |
| Lead Free / RoHS | — | Yes (per verified data) |