EPM570GT100C3N vs EPM570T100C3N Vergleich
Detaillierter Direktvergleich von EPM570GT100C3N von Altera und EPM570T100C3N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM570GT100C3N | EPM570T100C3N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $12,90 | $8,10 |
| Family | MAX II | MAX II |
| Series | MAX II G (Green) | — |
| Logic Elements | 570 | — |
| Macrocells | 440 | — |
| User I/O Pins | 76 | — |
| User Flash Memory | 8 Kbits | — |
| Propagation Delay (tPD max) | 5.4 ns | — |
| Core Voltage (VCCINT) | 1.71 V to 1.89 V (1.8 V typical) | — |
| I/O Voltage Standards | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) | — |
| Process Technology | 0.18 um | 0.18 µm Flash |
| Betriebstemperatur | 0C to 85C (TJ, commercial) | 0 °C to +85 °C (Commercial) |
| Gehäuse | 100-pin TQFP (14x14 mm) | 100-TQFP (T100) |
| Montageart | Surface Mount | Surface Mount |
| Programmable Type | In-System Programmable (Flash, non-volatile) | — |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | JTAG / IEEE 1149.1 boundary-scan |
| RoHS-Status | Lead free / RoHS Compliant | Compliant |
| Macro Cells | — | 440 |
| Logic Elements (LEs) | — | 570 |
| Maximum User I/Os | — | 76 |
| Pin-to-Pin Delay (tPD1) | — | 5.4 ns |
| Maximum Internal Frequency | — | 304 MHz |
| User Flash Memory (UFM) | — | 8 Kbits |
| Number of LABs | — | 57 |
| Supply Voltage - Core | — | 2.5 V / 3.3 V |
| I/O Standards Supported | — | 1.5 V, 1.8 V, 2.5 V, 3.3 V (MultiVolt) |
| In-System Programmable | — | Yes |
| Speed Grade | — | C3 |