EPM570T100C3N vs EPM570GT100C3N Vergleich
Detaillierter Direktvergleich von EPM570T100C3N von Intel und EPM570GT100C3N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM570T100C3N | EPM570GT100C3N |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $8,10 | $12,90 |
| Family | MAX II | MAX II |
| Macro Cells | 440 | — |
| Logic Elements (LEs) | 570 | — |
| Maximum User I/Os | 76 | — |
| Pin-to-Pin Delay (tPD1) | 5.4 ns | — |
| Maximum Internal Frequency | 304 MHz | — |
| User Flash Memory (UFM) | 8 Kbits | — |
| Number of LABs | 57 | — |
| Supply Voltage - Core | 2.5 V / 3.3 V | — |
| I/O Standards Supported | 1.5 V, 1.8 V, 2.5 V, 3.3 V (MultiVolt) | — |
| Process Technology | 0.18 µm Flash | 0.18 um |
| Gehäuse | 100-TQFP (T100) | 100-pin TQFP (14x14 mm) |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | 0 °C to +85 °C (Commercial) | 0C to 85C (TJ, commercial) |
| Programming Interface | JTAG / IEEE 1149.1 boundary-scan | JTAG (IEEE 1149.1) / ISP |
| In-System Programmable | Yes | — |
| RoHS-Status | Compliant | Lead free / RoHS Compliant |
| Speed Grade | C3 | — |
| Series | — | MAX II G (Green) |
| Logic Elements | — | 570 |
| Macrocells | — | 440 |
| User I/O Pins | — | 76 |
| User Flash Memory | — | 8 Kbits |
| Propagation Delay (tPD max) | — | 5.4 ns |
| Core Voltage (VCCINT) | — | 1.71 V to 1.89 V (1.8 V typical) |
| I/O Voltage Standards | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) |
| Programmable Type | — | In-System Programmable (Flash, non-volatile) |