EPM570T100C3N vs EPM570T100C4 Vergleich
Detaillierter Direktvergleich von EPM570T100C3N von Intel und EPM570T100C4 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM570T100C3N | EPM570T100C4 |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $8,10 | $9,40 |
| Family | MAX II | MAX II |
| Macro Cells | 440 | — |
| Logic Elements (LEs) | 570 | 570 |
| Maximum User I/Os | 76 | — |
| Pin-to-Pin Delay (tPD1) | 5.4 ns | — |
| Maximum Internal Frequency | 304 MHz | — |
| User Flash Memory (UFM) | 8 Kbits | — |
| Number of LABs | 57 | — |
| Supply Voltage - Core | 2.5 V / 3.3 V | — |
| I/O Standards Supported | 1.5 V, 1.8 V, 2.5 V, 3.3 V (MultiVolt) | — |
| Process Technology | 0.18 µm Flash | — |
| Gehäuse | 100-TQFP (T100) | TQFP-100 (T100), 14 x 14 mm |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | 0 °C to +85 °C (Commercial) | 0C to +85C (commercial) |
| Programming Interface | JTAG / IEEE 1149.1 boundary-scan | JTAG (IEEE 1149.1) - ISP |
| In-System Programmable | Yes | — |
| RoHS-Status | Compliant | Compliant |
| Speed Grade | C3 | — |
| Macrocells | — | 440 |
| Maximum User I/O Pins (this package) | — | 80 |
| Pin-to-Pin Propagation Delay (tPD) | — | 5.4 ns |
| User Flash Memory | — | 8 Kbits |
| General-Purpose SRAM | — | 4.4 Mbits |
| Core Voltage (VCCINT) | — | 1.8 V |
| I/O Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) |
| MSL-Level | — | [DATA_NEEDED: MSL Level] |
| On-chip Oscillator | — | Yes (3.3 MHz / 5.5 MHz selectable) |
| Internal Logic Analyzers / ISP | — | JTAG-based in-system programmable, no external boot PROM required |