EPM570T100I5 vs EPM240T100C5N Vergleich
Detaillierter Direktvergleich von EPM570T100I5 von Altera und EPM240T100C5N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM570T100I5 | EPM240T100C5N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $7,25 | $4,65 |
| Series | MAX II | — |
| Family | EPM570 (MAX II) | MAX II |
| Logic Elements (LEs) | 570 | 240 |
| Equivalent Macrocells | 440 | 192 |
| User I/Os | 76 | — |
| Propagation Delay (tPD) | 5.4 ns | — |
| User Flash Memory (UFM) | 8 Kbits | — |
| Process Technology | 0.18 micron, 6-layer-metal flash | 0.18 µm, 6-layer-metal flash |
| Gehäuse | TQFP-100 (14x14x1 mm) | 100-pin TQFP (T100), 14x14 mm |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | -40C to +100C (industrial) | 0 °C to +85 °C (commercial, 'C' suffix) |
| Core Supply Voltage | 3.0 V to 3.6 V | — |
| I/O Standards Supported | 1.5V / 1.8V / 2.5V / 3.3V LVCMOS/LVTTL | — |
| Programming Interface | JTAG (IEEE 1149.1), in-system programmable | JTAG (IEEE 1149.1) / ISP |
| Configuration Method | Non-volatile flash, instant-on | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance] | Compliant (lead-free) |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| On-Chip User Flash | — | 8 Kbits |
| Maximum User I/O Pins | — | 80 |
| Number of I/O Banks | — | 4 |
| Pin-to-Pin Delay (speed grade 5) | — | 4.7 ns |
| Maximum Internal Frequency | — | 201.1 MHz |
| Core Supply Voltage (VCCINT) | — | 2.5 V / 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) |