EPM7128AEFC100-5 vs EPM7128AET1100-7 Vergleich
Detaillierter Direktvergleich von EPM7128AEFC100-5 von Altera und EPM7128AET1100-7 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EPM7128AET1100-7 - 128-Macrocell MAX 7000A CPLD | Intel
EPM7128AET1100-7 ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPM7128AEFC100-5 | EPM7128AET1100-7 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $79,50 | $16,40 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Family | MAX 7000A | MAX 7000A (MAX 7000AE) |
| Logic Family / Base Number | EPM7128A | — |
| Macrocells | 128 | 128 |
| Usable Gates | 2,500 | 2,500 |
| Propagation Delay (tPD) | 5 ns | — |
| Internal Frequency (fMAX) | 192.3 MHz | — |
| User I/Os | 84 | — |
| Logic Family | CMOS | — |
| Versorgungsspannung | 3.3 V | — |
| Gehäuse | 100-ball FBGA (FineLine BGA) | TQFP-100 |
| Pin-Anzahl | 100 | — |
| Montageart | Surface Mount | Surface Mount |
| Programmable Type | EEPROM (In-System Programmable) | — |
| Betriebstemperatur | 0C to +70C (Commercial) | -40C to +85C (industrial) |
| JTAG Support | Yes (IEEE 1149.1 Boundary Scan) | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | ROHS3 Compliant |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| User I/O Pins | — | 84 |
| Logic Elements / LABs | — | [DATA_NEEDED: LAB count for 7128A] |
| Speed Grade | — | -7 (5 ns pin-to-pin) |
| Supply Voltage VCC | — | 5.0 V (typical) |
| I/O Voltage Tolerance | — | 3.3 V / 5.0 V |
| Configuration Memory | — | EEPROM (non-volatile, instant-on) |
| Programming Interface | — | IEEE 1149.1 JTAG / ByteBlaster |
| MSL-Level | — | 3 (168 hours, per JEDEC J-STD-020) |
| Lead-Free | — | Yes |
| Process Technology | — | CMOS, EEPROM-based |