EPM7128AETC100-10 vs EPM7128AETI100-7N Vergleich
Detaillierter Direktvergleich von EPM7128AETC100-10 von Intel und EPM7128AETI100-7N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM7128AETI100-7N - MAX 7000A CPLD 128 Macro 84 I/O | Intel/Altera
EPM7128AETI100-7N ObsoleteSpezifikationsvergleich
| Parameter | EPM7128AETC100-10 | EPM7128AETI100-7N |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $13,85 | $28,50 |
| Family | MAX 7000A | MAX 7000A CPLD |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 128 | — |
| User I/Os | 84 | — |
| Usable Gates | 2.5K | — |
| Logic Array Blocks (LABs) | 8 | — |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Supply Voltage (Core) | 3.3 V | — |
| I/O Tolerance | 5.0 V tolerant | — |
| Program Technology | EEPROM (in-system programmable) | — |
| Gehäuse | 100-pin TQFP (ET) | 100-pin TQFP (14x14 mm) |
| Betriebstemperatur | -40C to +85C (commercial/industrial) | -40C to +85C (Industrial) |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| RoHS-Status | Compliant | Compliant |
| Lebenszyklusstatus | Obsolete (migrate to MAX II or MAX V) | — |
| Series | — | MAX 7000A |
| Macro Cells | — | 128 |
| Number of Usable Gates | — | 2,500 |
| Number of I/O | — | 84 |
| Number of Logic Array Blocks (LABs) | — | 8 |
| Propagation Delay (tPD max) | — | 7 ns |
| Maximum Operating Frequency (fCNT) | — | 129.9 MHz |
| Supply Voltage (VCCINT) | — | 3.0 V to 3.6 V |
| I/O Bank Voltage (VCCIO) | — | 2.5 V / 3.3 V / 5.0 V (multi-volt I/O) |
| Process Technology | — | CMOS EEPROM |
| Montageart | — | Surface Mount |
| In-System Programmability | — | Yes (JTAG IEEE 1149.1) |