EPM7128AETC100-5N vs EPM7256AETC100-5N Vergleich
Detaillierter Direktvergleich von EPM7128AETC100-5N von Intel und EPM7256AETC100-5N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EPM7128AETC100-5N - 128-Macrocell MAX 7000A CPLD, 5ns | Intel / Altera
EPM7128AETC100-5N ✓ AktivAltera
EPM7256AETC100-5N - 256-Macro MAX 7000A CPLD, 5ns TQFP-100
EPM7256AETC100-5N ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPM7128AETC100-5N | EPM7256AETC100-5N |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $6,85 | $9,75 |
| Family | MAX 7000A | MAX 7000A |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Macrocells | 128 | — |
| User I/Os | 84 | 84 |
| Logic Gates (typical) | 2,500 | — |
| Pin-to-Pin Logic Delay (tPD) | 5 ns | — |
| Maximum Operating Frequency | 192.3 MHz | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Bank Supply Voltage (VCCIO) | 3.3 V or 2.5 V | — |
| 5V Tolerant Inputs | Yes (when VCCIO = 3.3 V) | — |
| Programmable Logic Type | EEPROM-based, in-system programmable | — |
| Programming Interface | JTAG (IEEE Std. 1149.1) | — |
| Gehäuse | 100-pin TQFP | TQFP-100 (1.0 mm pitch, 14x14 mm) |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | 0C to +70C (commercial) | 0C to +70C (Commercial) |
| RoHS-Status | Compliant | Compliant (lead-free) |
| Series | — | MAX 7000AE |
| Macro Cells | — | 256 |
| Usable Gates | — | 5000 (range 600 to 10000) |
| Logic Array Blocks (LABs) | — | 16 |
| Pin-to-Pin Delay (tPD) | — | 5.0 ns |
| Counter Frequency (fCNT) | — | up to 227.3 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V |
| MultiVolt I/O Support | — | 2.5 V / 3.3 V / 5.0 V |
| Program Memory | — | Internal EEPROM |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| MSL-Level | — | 3 (168 hours) |
| Process Technology | — | CMOS, EEPROM-based |
| Security Bit | — | Programmable |