EPM7128AETC144-10 vs EPM7128AETC144-10N Vergleich
Detaillierter Direktvergleich von EPM7128AETC144-10 von Altera und EPM7128AETC144-10N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM7128AETC144-10 | EPM7128AETC144-10N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $21,70 | $22,56 |
| Family | MAX 7000A | MAX 7000A |
| Macrocells | 128 | — |
| Usable Gates | 2,500 | — |
| Logic Array Blocks (LABs) | 8 | — |
| Maximum User I/Os | 36 | — |
| Pin-to-pin Logic Delay (tPD) | 10 ns | — |
| Maximum Internal Counter Frequency | 98 MHz | — |
| Supply Voltage (Core) | 3.3 V | — |
| I/O Voltage Tolerance | 2.5 V / 3.3 V / 5 V | — |
| Betriebstemperatur | 0C to +70C (Commercial) | 0 C to +70 C (commercial) |
| Gehäuse | 144-pin TQFP (also referred to as LQFP-144) | 144-pin TQFP (T144) |
| Programming Interface | JTAG (IEEE Std. 1149.1) and ByteBlaster | — |
| Non-volatile Memory | EEPROM, instant-on | — |
| Global Clocks / Global OE | 2 / 2 | — |
| Montageart | Surface Mount | Surface Mount |
| MSL-Level | MSL 3 (per JEDEC J-STD-020) | — |
| RoHS-Status | [DATA_NEEDED: rohs status from manufacturer] | [DATA_NEEDED: rohs status] |
| Number of Macros | — | 128 |
| Logic Gates | — | 2,500 usable gates |
| Number of I/O Pins | — | 100 (max user I/O) |
| Propagation Delay (tPD) | — | 10 ns (grade -10) |
| Internal Frequency | — | Up to 250 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Standards | — | 2.5 V / 3.3 V / 5 V multiVolt |
| Configuration Memory | — | CMOS EEPROM (non-volatile) |
| JTAG Support | — | IEEE 1149.1 compliant boundary-scan |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |