EPM7128AETI100-7N vs EPM7128AETC100-10N Vergleich
Detaillierter Direktvergleich von EPM7128AETI100-7N von Altera und EPM7128AETC100-10N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM7128AETI100-7N - MAX 7000A CPLD 128 Macro 84 I/O | Intel/Altera
EPM7128AETI100-7N ObsoleteIntel
EPM7128AETC100-10N - MAX 7000AE 128-Macrocell CPLD | Intel | TQFP-100
EPM7128AETC100-10N ObsoleteSpezifikationsvergleich
| Parameter | EPM7128AETI100-7N | EPM7128AETC100-10N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $28,50 | $9,95 |
| Series | MAX 7000A | EPM7128AE |
| Family | MAX 7000A CPLD | MAX 7000AE |
| Macro Cells | 128 | — |
| Number of Usable Gates | 2,500 | — |
| Number of I/O | 84 | — |
| Number of Logic Array Blocks (LABs) | 8 | — |
| Propagation Delay (tPD max) | 7 ns | — |
| Maximum Operating Frequency (fCNT) | 129.9 MHz | — |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V | — |
| I/O Bank Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (multi-volt I/O) | — |
| Process Technology | CMOS EEPROM | CMOS EEPROM |
| Gehäuse | 100-pin TQFP (14x14 mm) | TQFP-100 |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | -40C to +85C (Industrial) | 0C to +70C (commercial) |
| In-System Programmability | Yes (JTAG IEEE 1149.1) | — |
| RoHS-Status | Compliant | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 128 |
| Usable Gates | — | 2500 |
| Logic Array Blocks | — | 16 |
| User I/Os | — | 84 |
| Supply Voltage (Core) | — | 3.3 V |
| I/O Tolerance | — | 5.0 V tolerant |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Speed Grade | — | -10 |
| Maximum Frequency | — | [DATA_NEEDED: maximum toggle frequency] |
| Programming | — | JTAG (IEEE 1149.1) ISP / EEPROM |
| Lead-Free / RoHS | — | Yes (N suffix) |
| Architecture | — | Multiple Array MatriX (MAX) - 2nd generation |
| PCI Compliance | — | Yes (33 MHz, -10 grade per PCI SIG 2.2) |