EPM7128ELC84-12 vs EPM7096LC84-10 Vergleich
Detaillierter Direktvergleich von EPM7128ELC84-12 von Altera und EPM7096LC84-10 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM7128ELC84-12 | EPM7096LC84-10 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $10,40 | $5,10 |
| Family | MAX 7000 (MAX 7000E series) | MAX 7000 |
| Logic Family | CMOS, EEPROM-based | — |
| Usable Gates | 2,500 | — |
| Macrocells | 128 | 96 |
| Logic Array Blocks (LABs) | 8 | 4 |
| User I/Os | 84 | — |
| Propagation Delay (tpd1) | 12 ns | — |
| Internal Global Clock Frequency | 90.9 MHz | — |
| Setup Time | 4.5 ns | — |
| Supply Voltage (VCCINT / VCCIO) | 5 V (4.75 V to 5.25 V) | — |
| Betriebstemperatur | 0C to +70C (commercial) | — |
| Gehäuse | 84-pin PLCC (J-Lead, QCCJ) | 84-PLCC (J-Lead) |
| Montageart | Surface Mount (PLCC socket compatible) | Surface Mount (PLCC socket or SMT) |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | — |
| Pin-Anzahl | 84 | — |
| RoHS-Status | Non-compliant (legacy 5V part, SnPb finish) | [DATA_NEEDED: RoHS status] |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Maximum User I/O Pins | — | 36 |
| Propagation Delay (tPD) | — | 10 ns (-10 speed grade) |
| Process Technology | — | EEPROM-based, 5.0 V low-power CMOS (L) |
| Supply Voltage (VCC) | — | 5.0 V nominal (4.75 V - 5.25 V) |
| In-System Programmability | — | Yes, via IEEE 1149.1 JTAG |
| MultiVolt I/O | — | 2.5 V / 3.3 V / 5.0 V mixed-voltage interface |
| Betriebstemperaturbereich | — | 0C to +70C (Commercial, 'C') |
| Configuration Memory | — | Non-volatile EEPROM (instant-on) |
| Programmable Interconnect | — | PIA (Programmable Interconnect Array) |