EPM7128SLI84-10N vs EPM7128SLC84-15 Vergleich
Detaillierter Direktvergleich von EPM7128SLI84-10N von Altera und EPM7128SLC84-15 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM7128SLI84-10N - MAX 7000S CPLD 128 Macro 10ns 84-PLCC | Intel / Altera
EPM7128SLI84-10N NrndIntel
EPM7128SLC84-15 - 128-Macrocell MAX 7000S CPLD, 84-PLCC | Intel / Altera
EPM7128SLC84-15 ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPM7128SLI84-10N | EPM7128SLC84-15 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $8,45 | $10,40 |
| Family | MAX 7000S | MAX 7000S |
| Logic Cells / Macro Cells | 128 macro cells | — |
| Usable Gates | 2,500 | 2,500 |
| Number of Logic Elements / Blocks | 16 Logic Array Blocks (LABs) | — |
| User I/Os | 68 | 68 (in 84-PLCC) |
| Propagation Delay (tPD) | 10 ns | 15 ns |
| Maximum Frequency (fMAX) | 125 MHz | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5 V typical) | 5 V |
| I/O Voltage Tolerance | 3.3 V / 5 V MultiVolt I/O | — |
| Process Technology | CMOS EEPROM | — |
| Programmability | In-system programmable (ISP), non-volatile EEPROM | — |
| Boundary-Scan (JTAG) | IEEE Std 1149.1 compliant | — |
| Gehäuse | 84-pin PLCC (J-Lead) | 84-Pin PLCC (J-Lead, J84) |
| Montageart | Surface Mount | Surface Mount / Socketed (PLCC-84 socket) |
| Betriebstemperatur | -40 C to +85 C (Industrial) | 0C to +70C (commercial) |
| RoHS-Status | [DATA_NEEDED: RoHS compliance per latest Intel/Altera declaration] | Non-RoHS (legacy 5V part) |
| Lead-Free | [DATA_NEEDED: lead-free per latest Intel/Altera declaration] | — |
| Device Type | — | CPLD - Complex Programmable Logic Device |
| Macrocells | — | 128 |
| Speed Grade | — | -15 (15 ns pin-to-pin delay) |
| Maximum Internal Frequency (fMAX) | — | 76.9 MHz |
| Logic Family / Process | — | CMOS, 5V, EEPROM |
| I/O Standard Support | — | 5.0 V TTL/CMOS (multi-volt I/O compatible with 3.3V) |
| Programming Interface | — | JTAG (IEEE Std. 1149.1), in-system programmable |
| Configuration Memory | — | Non-volatile EEPROM (instant-on, no boot PROM) |