EPM7128SLI84-10N vs EPM7128SLI84-15 Vergleich
Detaillierter Direktvergleich von EPM7128SLI84-10N von Altera und EPM7128SLI84-15 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM7128SLI84-10N - MAX 7000S CPLD 128 Macro 10ns 84-PLCC | Intel / Altera
EPM7128SLI84-10N NrndSpezifikationsvergleich
| Parameter | EPM7128SLI84-10N | EPM7128SLI84-15 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $8,45 | $8,40 |
| Family | MAX 7000S | MAX 7000 |
| Logic Cells / Macro Cells | 128 macro cells | — |
| Usable Gates | 2,500 | — |
| Number of Logic Elements / Blocks | 16 Logic Array Blocks (LABs) | — |
| User I/Os | 68 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Frequency (fMAX) | 125 MHz | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5 V typical) | 4.5 V to 5.5 V |
| I/O Voltage Tolerance | 3.3 V / 5 V MultiVolt I/O | 3.3 V or 5.0 V (configurable) |
| Process Technology | CMOS EEPROM | CMOS EEPROM |
| Programmability | In-system programmable (ISP), non-volatile EEPROM | — |
| Boundary-Scan (JTAG) | IEEE Std 1149.1 compliant | — |
| Gehäuse | 84-pin PLCC (J-Lead) | PLCC-84 (Plastic Leaded Chip Carrier, J-lead) |
| Montageart | Surface Mount | Surface Mount (PLCC socket compatible) |
| Betriebstemperatur | -40 C to +85 C (Industrial) | -40 C to +85 C (Industrial grade, 'I' suffix) |
| RoHS-Status | [DATA_NEEDED: RoHS compliance per latest Intel/Altera declaration] | [DATA_NEEDED: rohs status] |
| Lead-Free | [DATA_NEEDED: lead-free per latest Intel/Altera declaration] | — |
| Series | — | EPM7128S |
| Device Type | — | EE PLD (CPLD) |
| Macrocells | — | 128 |
| Logic Elements | — | 250 (approx.) |
| User I/O Pins | — | 84 (68 in 84-pin PLCC per some sources) |
| Propagation Delay (tpd) | — | 15 ns |
| Program Memory Type | — | EEPROM (in-system programmable) |
| Pin-Anzahl | — | 84 |
| Programming Interface | — | JTAG (IEEE 1149.1) |
| Maximum User Flash Endurance | — | 100 program/erase cycles |
| Data Retention | — | 20 years |