EPM7128SQC100-10F vs EPM7128ATC100-10 Vergleich
Detaillierter Direktvergleich von EPM7128SQC100-10F von Altera und EPM7128ATC100-10 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM7128SQC100-10F - 128-Macrocell MAX 7000 CPLD, 10ns, 100-PQFP | Altera (Intel)
EPM7128SQC100-10F ✓ AktivAltera
EPM7128ATC100-10 - MAX 7000A CPLD, 128 Macrocells, 10ns TQFP-100 | Altera
EPM7128ATC100-10 ObsoleteSpezifikationsvergleich
| Parameter | EPM7128SQC100-10F | EPM7128ATC100-10 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $4,95 | $4,95 |
| Family | MAX 7000S | MAX 7000A |
| Product Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 2,500 | 2.5K |
| Macrocells | 128 | 128 |
| Logic Array Blocks (LABs) | 8 | 4 |
| User I/Os | 84 | — |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Counter Frequency | 100 MHz | — |
| Supply Voltage (VCCINT) | 5 V | — |
| Process Technology | CMOS EEPROM | — |
| Programmability | In-System Programmable (ISP) via JTAG (IEEE 1149.1) | — |
| Gehäuse | 100-pin PQFP (Plastic Quad Flat Pack) | 100-pin TQFP (TC100) |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Lead-Free (F suffix) | Yes (Pb-free finish) | — |
| RoHS-Status | Compliant (F suffix variant) | [DATA_NEEDED: RoHS compliance] |
| Architecture | — | Multiple Array MatriX (MAX) |
| User I/O Pins | — | 68 |
| Pin-to-Pin Logic Delay | — | 4.5 ns |
| Counter Frequency (max) | — | 227.3 MHz |
| Speed Grade | — | -10 (10 ns) |
| Core Supply Voltage | — | 3.3 V |
| I/O Logic Level Support | — | 5.0 V / 3.3 V / 2.5 V (MultiVolt) |
| Program Memory | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |