EPM7128SQC100-10N vs EPM7128AETC100-10 Vergleich
Detaillierter Direktvergleich von EPM7128SQC100-10N von Altera und EPM7128AETC100-10 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM7128SQC100-10N | EPM7128AETC100-10 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $14,95 | $13,85 |
| Family | MAX 7000 | MAX 7000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 | — |
| Usable Gates | 2,500 | 2.5K |
| Logic Array Blocks (LABs) | 8 (16 macro cells each) | 8 |
| User I/O Pins | 84 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Frequency | 100 MHz | — |
| Supply Voltage (VCCINT) | 5 V (4.75 V to 5.25 V) | — |
| I/O Voltage Tolerance | 3.3 V or 5 V (MultiVolt interface) | — |
| Gehäuse | 100-pin PQFP (BQFP) | 100-pin TQFP (ET) |
| Configuration Memory | EEPROM (non-volatile) | — |
| Programming Interface | JTAG (IEEE Std 1149.1), 4-pin | — |
| Betriebstemperatur | -40C to +85C (industrial) | -40C to +85C (commercial/industrial) |
| Montageart | Surface Mount | — |
| Lead-Free / RoHS Status | Lead-free (N suffix) | — |
| Architecture Generation | Second-generation MAX | — |
| Macrocells | — | 128 |
| User I/Os | — | 84 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Supply Voltage (Core) | — | 3.3 V |
| I/O Tolerance | — | 5.0 V tolerant |
| Program Technology | — | EEPROM (in-system programmable) |
| JTAG Support | — | IEEE 1149.1 boundary-scan |
| RoHS-Status | — | Compliant |
| Lebenszyklusstatus | — | Obsolete (migrate to MAX II or MAX V) |