EPM7128SQC100-10N vs EPM7128STC100-10 Vergleich
Detaillierter Direktvergleich von EPM7128SQC100-10N von Altera und EPM7128STC100-10 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM7128STC100-10 - 128-Macro MAX 7000S CPLD, 10ns TQFP-100 | Intel / Altera
EPM7128STC100-10 ObsoleteSpezifikationsvergleich
| Parameter | EPM7128SQC100-10N | EPM7128STC100-10 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $14,95 | $7,10 |
| Family | MAX 7000 | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 | 128 |
| Usable Gates | 2,500 | 2,500 |
| Logic Array Blocks (LABs) | 8 (16 macro cells each) | — |
| User I/O Pins | 84 | — |
| Propagation Delay (tPD) | 10 ns | 10 ns |
| Maximum Frequency | 100 MHz | — |
| Supply Voltage (VCCINT) | 5 V (4.75 V to 5.25 V) | 5 V |
| I/O Voltage Tolerance | 3.3 V or 5 V (MultiVolt interface) | — |
| Gehäuse | 100-pin PQFP (BQFP) | TQFP-100 (C100) |
| Configuration Memory | EEPROM (non-volatile) | — |
| Programming Interface | JTAG (IEEE Std 1149.1), 4-pin | — |
| Betriebstemperatur | -40C to +85C (industrial) | 0C to +70C (commercial) |
| Montageart | Surface Mount | Surface Mount |
| Lead-Free / RoHS Status | Lead-free (N suffix) | — |
| Architecture Generation | Second-generation MAX | — |
| User I/Os | — | 84 |
| Logic Array Blocks | — | 8 (16 macrocells per LAB) |
| Internal Counter Frequency (fCNT) | — | 100 MHz |
| Logic Family | — | CMOS |
| MultiVolt I/O Voltage | — | 3.3 V / 5 V |
| Pin-Anzahl | — | 100 |
| Programmability | — | In-System Programmable (JTAG, IEEE 1149.1), EEPROM |
| RoHS-Status | — | [DATA_NEEDED: RoHS compliance status not in provided data] |