EPM7128STI100-10N vs EPM7128STC100-10N Vergleich
Detaillierter Direktvergleich von EPM7128STI100-10N von Altera und EPM7128STC100-10N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM7128STI100-10N - 128-Macrocell CPLD, 10ns, 100-pin TQFP | Altera
EPM7128STI100-10N ObsoleteAltera
EPM7128STC100-10N - MAX 7000S CPLD 128-Macrocell 10ns TQFP-100 | Altera
EPM7128STC100-10N NrndSpezifikationsvergleich
| Parameter | EPM7128STI100-10N | EPM7128STC100-10N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,85 | $9,30 |
| Family | MAX 7000S | MAX 7000S |
| Architecture | CMOS EEPROM-based CPLD | — |
| Macrocells | 128 | 128 |
| Usable Gates | 2,500 (up to 5,000 family max) | 2,500 |
| Logic Array Blocks (LABs) | 8 | 8 (16 macrocells each) |
| Maximum User I/O | 84 | — |
| Pin-to-Pin Logic Delay (tPD) | 10 ns | — |
| Maximum Counter Frequency | 175.4 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| In-System Programmability | Yes (JTAG IEEE 1149.1) | Yes (IEEE 1149.1 JTAG) |
| JTAG Boundary-Scan | Yes (BST) | — |
| Gehäuse | 100-pin TQFP | 100-pin TQFP (14 x 14 x 1 mm) |
| Betriebstemperatur | -40C to +85C (Industrial) | 0 C to +70 C (commercial) |
| Montageart | Surface Mount | Surface Mount |
| MSL-Level | [DATA_NEEDED: MSL level] | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | Compliant (Pb-free "N" suffix) |
| Open-Drain I/O Option | Available (per MAX 7000A feature set) | — |
| Product Type | — | CPLD - Complex Programmable Logic Device |
| User I/Os | — | 84 |
| Propagation Delay (tPD) | — | 10 ns |
| Internal Frequency (fMAX) | — | 100 MHz |
| Supply Voltage (VCCINT) | — | 5 V |
| I/O Voltage (VCCIO) | — | 3.3 V or 5 V (MultiVolt) |
| Process Technology | — | CMOS EEPROM |
| Lead-Free | — | Yes |