EPM7160SLC84-15 vs EPM7160SLC84-10 Vergleich
Detaillierter Direktvergleich von EPM7160SLC84-15 von Altera und EPM7160SLC84-10 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM7160SLC84-15 | EPM7160SLC84-10 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $10,80 | $35,77 |
| Family | MAX 7000 | MAX 7000S |
| Macrocells | 160 | 160 |
| Usable Gates | 3,200 | 3,200 |
| Maximum Propagation Delay | 15 ns | — |
| Maximum User I/O Pins | 64 | 64 |
| Supply Voltage (VCCINT/VCIO) | 4.75 V to 5.25 V (5 V nominal) | — |
| I/O Logic Level | Configurable 3.3 V or 5 V | — |
| Technology | CMOS, EEPROM configuration | EEPROM-based CMOS |
| Package Type | PLCC-84 (PQCC84, JEDEC S-PQCC-J84) | — |
| Terminal Pitch | 1.270 mm | — |
| Montageart | Surface Mount (PLCC socket or direct solder) | Surface Mount |
| Betriebstemperatur | 0 C to 70 C | 0C to +70C (Commercial) |
| Programming Interface | JTAG (IEEE 1149.1) in-system programmable | — |
| RoHS-Status | Not RoHS compliant (contains lead, SnPb finish typical) | [DATA_NEEDED: RoHS status] |
| Lifecycle | Obsolete / last-time-buy (per Altera/Intel PDN) | — |
| Logic Array Blocks (LABs) | — | 4 |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Operating Frequency | — | 100 MHz |
| Supply Voltage (VCCINT/VCCIO) | — | 5.0 V |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG, 5.0 V) |
| Gehäuse | — | 84-Pin PLCC (J-Lead) |
| JTAG Boundary Scan | — | Yes (IEEE Std. 1149.1 compliant) |