EPM7160STC100-6N vs EPM7160STC100-10F Vergleich
Detaillierter Direktvergleich von EPM7160STC100-6N von Altera und EPM7160STC100-10F von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM7160STC100-6N | EPM7160STC100-10F |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $14,20 | $9,95 |
| Family | MAX 7000S | MAX 7000S |
| Logic Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 160 | — |
| User I/Os | 84 | — |
| Gates (typical) | 3,200 | — |
| Propagation Delay (tPD) | 6 ns | 10 ns |
| Internal Frequency | 149.3 MHz (max) | — |
| Versorgungsspannung | 5 V | — |
| Program Memory Type | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Gehäuse | TQFP-100 (T100) | 100-pin TQFP (1.0 mm height, lead-free) |
| Package Code | LFQFP, S Gull-Wing | — |
| Betriebstemperatur | 0 °C to +70 °C (Commercial) | 0 °C to +70 °C (commercial) |
| Logic Family | CMOS | — |
| I/O Banks | [DATA_NEEDED: I/O bank count] | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance] | Lead-free (suffix F indicates Pb-free) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 160 |
| Usable Gates | — | 3,200 |
| Maximum User I/O Pins | — | 84 |
| Dedicated Inputs | — | 4 |
| Maximum Frequency (fMAX) | — | 100 MHz |
| Supply Voltage (VCCINT) | — | 5.0 V |
| Process Technology | — | CMOS, EEPROM-based |
| Programmability | — | In-System Programmable (ISP) via JTAG (IEEE 1149.1) |
| Montageart | — | Surface Mount |