EPM7192EGM160-20 vs EPM7192EGM160-15 Vergleich
Detaillierter Direktvergleich von EPM7192EGM160-20 von Altera und EPM7192EGM160-15 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM7192EGM160-20 - 192-Macrocell MAX 7000 CPLD, 20ns PGA-160 | Altera
EPM7192EGM160-20 ObsoleteSpezifikationsvergleich
| Parameter | EPM7192EGM160-20 | EPM7192EGM160-15 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $15,60 | $36,80 |
| Family | MAX 7000 | MAX 7000 |
| Device Type | EE CMOS CPLD (Electrically Erasable) | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 (16 macrocells each) |
| Usable Gates | 600 to 5,000 | 3750 |
| Maximum User I/O Pins | 120 | — |
| Gehäuse | PGA-160 (160-pin Pin Grid Array) | 160-pin PGA (Pin Grid Array), ceramic |
| Speed Grade | -20 (20 ns pin-to-pin) | — |
| Pin-to-Pin Propagation Delay | 20 ns | — |
| Counter Frequency (max) | 175.4 MHz | — |
| I/O Standards | 3.3 V or 5 V configurable | — |
| Global Clock Inputs | 2 (GCLK1, GCLK2) | — |
| In-System Programming | Yes (JTAG IEEE 1149.1) | — |
| Program/Erase Endurance | 100 cycles (EEPROM) | — |
| Betriebstemperatur | -40C to +125C (industrial) | [DATA_NEEDED: operating temperature range] |
| Technology Node | CMOS, second-generation MAX architecture | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Sub-family | — | MAX 7000E |
| Device | — | EPM7192E |
| User I/O Pins | — | 124 |
| Pin-to-Pin Logic Delay (tPD) | — | 15 ns |
| Supply Voltage (Core) | — | 5 V ±5% |
| I/O Voltage | — | 3.3 V or 5 V configurable |
| Technology | — | CMOS EEPROM (0.5 µm) |
| Programming Interface | — | JTAG (ByteBlaster / BitBlaster) |
| Montageart | — | Through-hole (PGA socket) |