EPM7192SQC160-10 vs EPM7192SQC160-15 Vergleich
Detaillierter Direktvergleich von EPM7192SQC160-10 von Altera und EPM7192SQC160-15 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM7192SQC160-10 - 192-Macro MAX 7000S CPLD, 100MHz, PQFP-160 | Intel / Altera
EPM7192SQC160-10 NrndSpezifikationsvergleich
| Parameter | EPM7192SQC160-10 | EPM7192SQC160-15 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $18,25 | $8,75 |
| Family | MAX 7000S | MAX 7000S |
| Macrocells | 192 | — |
| Logic Array Blocks (LABs) | 4 | — |
| User I/Os | 124 | — |
| Usable Gates | 3750 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Operating Frequency | 100 MHz | 76.9 MHz |
| Supply Voltage (VCCINT) | 5.0 V | — |
| Program Memory Type | EEPROM | — |
| In-System Programmability | Yes (JTAG IEEE 1149.1) | — |
| Gehäuse | PQFP-160 (SQC) 28x28 mm | PQFP-160 |
| Pin/Package Type | Surface Mount, Gull-Wing | — |
| Operating Temperature (Commercial) | 0C to +70C | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | — |
| Lead Finish | [DATA_NEEDED: lead finish] | — |
| Device Type | — | CPLD - Complex Programmable Logic Device |
| Number of Macrocells | — | 192 |
| Number of Logic Array Blocks | — | 4 |
| Number of Usable Gates | — | 3750 |
| User I/O Pins | — | 124 |
| Pin-to-Pin Logic Delay (tPD) | — | 15 ns |
| Versorgungsspannung | — | 5.0 V |
| Programmability | — | In-System (ISP) via JTAG IEEE Std 1149.1 |
| Configuration Memory | — | EEPROM, non-volatile |
| Montageart | — | Surface Mount |
| Betriebstemperaturbereich | — | [DATA_NEEDED: operating temperature range] |
| Process Technology | — | CMOS, EEPROM-based |