EPM7192SQC160-10N vs EPM7192SQC160-7N Vergleich
Detaillierter Direktvergleich von EPM7192SQC160-10N von Altera und EPM7192SQC160-7N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM7192SQC160-10N - 192-Macrocell MAX 7000S CPLD, 10ns, 160-Pin PQFP | Altera
EPM7192SQC160-10N NrndAltera
EPM7192SQC160-7N - MAX 7000S 192-Macro CPLD, 7.5ns, PQFP-160 | Altera
EPM7192SQC160-7N ObsoleteSpezifikationsvergleich
| Parameter | EPM7192SQC160-10N | EPM7192SQC160-7N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,95 | $9,60 |
| Series | MAX 7000S | — |
| Family | MAX 7000 | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 192 | — |
| Logic Array Blocks (LABs) | 12 | — |
| Usable Gates | 3,750 | 3,750 |
| User I/O Pins | 124 | — |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Operating Frequency | 100 MHz | — |
| Supply Voltage (VCCINT) | 5.0 V | 5.0 V |
| Process Technology | 0.30 µm CMOS EEPROM | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Gehäuse / Bauform | 160-BQFP (PQFP, 0.65 mm pitch) | — |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | [DATA_NEEDED: commercial/industrial grade] | 0 C to 70 C (Commercial) |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | Compliant (Pb-free terminal finish) |
| Logic Family | — | CMOS |
| Macro Cells | — | 192 |
| User I/Os | — | 124 |
| Propagation Delay (tPD) | — | 7.5 ns |
| Internal Counter Frequency | — | 167 MHz |
| Pin-Anzahl | — | 160 |
| Package Type | — | PQFP (Plastic Quad Flat Pack) |
| I/O Voltage (VCCIO) | — | 3.3 V / 5.0 V selectable |
| Programmability | — | EEPROM, In-System (JTAG ISP) |
| JTAG Support | — | IEEE 1149.1 Boundary Scan |
| Lead-Free (Pb-Free) | — | Yes (N suffix) |