EPM7256AQC208-7 vs EPM7256AQI208-10 Vergleich
Detaillierter Direktvergleich von EPM7256AQC208-7 von Altera und EPM7256AQI208-10 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM7256AQC208-7 | EPM7256AQI208-10 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $27,20 | $13,22 |
| Family | MAX 7000A | MAX 7000A |
| Programmable Type | In System Programmable (ISP), EEPROM-based | — |
| Macrocells | 256 | 256 |
| Usable Gates | 5,000 | 5,000 |
| Logic Array Blocks (LABs) | 16 | 16 |
| Maximum User I/O Pins | 164 | — |
| Pin-to-Pin Logic Delay (tPD) | 7 ns | — |
| Maximum Counter Frequency | 125 MHz | 227.3 MHz |
| Internal Toggle Frequency | 227.3 MHz | — |
| Supply Voltage - Internal | 3.0 V to 3.6 V | — |
| I/O Voltage Compatibility | 5.0 V, 3.3 V, 2.5 V (MultiVolt I/O) | — |
| Gehäuse | 208-Pin PQFP (28 x 28 mm) | PQFP-208 |
| Supplier Device Package | 208-PQFP (28x28) | — |
| Montageart | Surface Mount | — |
| Betriebstemperaturbereich | 0C to +70C (commercial) | — |
| JTAG Interface | IEEE 1149.1 (JTAG) boundary scan | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| Speed Grade | -7 | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | Compliant (lead-free per distributor data) |
| MSL-Level | [DATA_NEEDED: MSL level] | — |
| User I/O Pins | — | 68 |
| Pin-to-Pin Propagation Delay | — | 10 ns |
| Maximum Internal Frequency | — | 93.5 MHz |
| Supply Voltage (Core) | — | 3.3 V |
| I/O Logic Compatibility | — | 5.0 V, 3.3 V, 2.5 V (MultiVolt) |
| Programmability | — | EEPROM, in-system via JTAG (IEEE 1149.1) |
| Betriebstemperatur | — | -40C to +85C (industrial) |
| Process Technology | — | CMOS, EEPROM-based |