EPM7256SQC208-15 vs EPM7256BQC208-7 Vergleich
Detaillierter Direktvergleich von EPM7256SQC208-15 von Altera und EPM7256BQC208-7 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM7256SQC208-15 | EPM7256BQC208-7 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $3,65 | $9,75 |
| Family | MAX 7000S | MAX 7000B |
| Series | EPM7256 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Macrocells | 256 | — |
| Logic Array Blocks (LABs) | 16 | — |
| Usable Gates | 5000 | 5,000 |
| User I/O Pins | 164 | — |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V | — |
| Betriebstemperaturbereich | 0 C to +70 C (Commercial) | — |
| Gehäuse | 208-pin PQFP (28x28 mm) | 208-pin PQFP |
| Montageart | Surface Mount | Surface Mount |
| Programmable Power Mode | Yes (per-macrocell turbo-bit) | — |
| JTAG (IEEE 1149.1) Boundary-Scan | Yes | — |
| In-System Programmability (ISP) | Yes | — |
| Configuration Memory | EEPROM (non-volatile) | Non-volatile EEPROM |
| RoHS-Status | Contains lead / RoHS non-compliant (per third-party listing) | Compliant per distributor listings |
| Lead-Free Status | Contains lead | — |
| Macro Cells | — | 256 |
| User I/Os | — | 164 |
| Logic Elements / LABs | — | 16 Logic Array Blocks |
| Maximum Internal Frequency | — | 126.6 MHz |
| Propagation Delay (tPD) | — | 7.5 ns (-7 speed grade) |
| Core Supply Voltage | — | 2.5 V |
| Betriebstemperatur | — | 0C to +90C (commercial) |
| JTAG / Boundary Scan | — | IEEE 1149.1 compliant |
| In-System Programmability | — | Yes (via JTAG) |