EPM7256SQC208-7N vs EPM7256SQC208-7 Vergleich
Detaillierter Direktvergleich von EPM7256SQC208-7N von Altera und EPM7256SQC208-7 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM7256SQC208-7N | EPM7256SQC208-7 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $27,20 | $0,00 |
| Family | MAX 7000S | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 256 | 256 |
| Usable Gates | 5,000 | 5,000 |
| Logic Array Blocks (LABs) | 16 | — |
| User I/O Pins | 164 | 164 |
| Speed Grade | -7 (7.5 ns pin-to-pin) | -7 (7.5 ns) |
| Maximum Frequency | 128.2 MHz | — |
| Supply Voltage (VCC) | 5 V | 5.0 V |
| Technology | CMOS EEPROM | — |
| Configuration Memory | Non-volatile EEPROM (no external config needed) | — |
| Gehäuse | 208-pin PQFP (Plastic Quad Flat Pack) | 208-pin PQFP (28 x 28 mm, 0.5 mm pitch) |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | Commercial (0C to +70C) | — |
| JTAG Interface | IEEE 1149.1 boundary-scan (ISP capable) | — |
| Minimum DC Input Voltage | -0.5 V | -0.5 V |
| Input Undershoot Tolerance | -2.0 V for <100 mA, <20 ns | -2.0 V for <100 mA, <20 ns |
| RoHS-Status | Compliant (N suffix = lead-free) | [DATA_NEEDED: RoHS status] |
| Pin-to-Pin Delay (tPD) | 7.5 ns | — |
| Open-Drain Output | Optional per I/O pin | — |
| Device Family | — | MAX 7000S (EPM7256S) |
| Propagation Delay (tPD) | — | 7.5 ns |
| Maximum Operating Frequency (fMAX) | — | 128.2 MHz |
| Configuration Technology | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Betriebstemperaturbereich | — | Commercial (0C to +70C) |
| MSL-Level | — | [DATA_NEEDED: MSL level] |
| Logic Levels | — | 5.0 V CMOS/TTL compatible |