EPM7256SQI208-10 vs EPM7256SQC208-15N Vergleich
Detaillierter Direktvergleich von EPM7256SQI208-10 von Altera und EPM7256SQC208-15N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM7256SQI208-10 | EPM7256SQC208-15N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $0,40 | $0,00 |
| Device Family | MAX 7000 (EPM7256) | — |
| Macrocells | 256 | 256 |
| Usable Gates | 5000 | — |
| Logic Array Blocks | 16 | 16 macrocells per LAB |
| Maximum User I/O Pins | 164 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Supply Voltage Range | 4.5 V to 5.5 V | — |
| Technology | CMOS EEPROM | — |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) |
| In-System Programmable | Yes (IEEE 1149.1 JTAG) | — |
| Gehäuse | 208-pin PQFP (QFP208) | 208-pin PQFP |
| Package Body Material | Plastic/Epoxy | — |
| Terminal Form | Gull Wing | — |
| Betriebstemperaturbereich | -40 C to +85 C (Industrial) | — |
| Montageart | Surface Mount | Surface Mount |
| RoHS-Status | [DATA_NEEDED: RoHS status] | Lead free / RoHS Compliant |
| JESD-30 Package Code | S-PQFP-G208 | — |
| JESD-609 Terminal Finish Code | E3 | — |
| Series | — | MAX 7000S |
| User I/O Pins | — | 164 |
| Pin-to-Pin Delay | — | 15 ns (speed grade -15) |
| Versorgungsspannung | — | 5 V |
| JTAG Interface | — | IEEE 1149.1 boundary-scan |
| In-System Programmability | — | Yes (ISP) |
| Betriebstemperatur | — | [DATA_NEEDED: operating temperature range] |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Speed Grade | — | -15 |
| Product Category | — | CPLD - Complex Programmable Logic Devices |
| Manufacturer | — | Altera (Intel Programmable Solutions Group) |