EPM9320ARC208-10N vs EPM9320ARC208-10 Vergleich
Detaillierter Direktvergleich von EPM9320ARC208-10N von Altera und EPM9320ARC208-10 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM9320ARC208-10 - MAX 9000 CPLD, 320 Macro, 10ns | Altera
EPM9320ARC208-10 ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPM9320ARC208-10N | EPM9320ARC208-10 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $19,45 | $21,40 |
| Family | MAX 9000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 320 | — |
| Logic Gates | 6,000 gates | — |
| Logic Array Blocks (LABs) | 16 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Frequency | 144.9 MHz | 144.9 MHz |
| Supply Voltage (VCC) | 5 V | — |
| User I/O Pins | 168 | — |
| Dedicated Input Pins | 12 | — |
| Gehäuse | 208-pin RQFP (BFQFP with exposed pad) | RQFP-208 (Power Quad Flat Pack) |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | 0C to +70C (Commercial) | [DATA_NEEDED: operating temperature range] |
| Programming Interface | IEEE Std. 1149.1 JTAG | — |
| Configuration Memory | Non-volatile EEPROM | — |
| RoHS-Status | Compliant (lead-free 'N' suffix) | [DATA_NEEDED: RoHS compliance status] |
| Device Family | — | MAX 9000 |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 320 |
| Usable Gates | — | 6,000 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Versorgungsspannung | — | 5.0 V |
| Logic Blocks (LABs) | — | 16 |
| Programmability | — | EEPROM, in-system programmable via JTAG |
| JTAG Support | — | IEEE Std. 1149.1 compliant |
| Speed/Power Optimization | — | Per-macrocell programmable, 50% power mode available |