EPM9320ARI208-10N vs EPM9320RC208-15N Vergleich
Detaillierter Direktvergleich von EPM9320ARI208-10N von Altera und EPM9320RC208-15N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM9320ARI208-10N - MAX 9000 CPLD, 320 Macrocells, 208-RQFP | Altera
EPM9320ARI208-10N ObsoleteSpezifikationsvergleich
| Parameter | EPM9320ARI208-10N | EPM9320RC208-15N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $16,20 | $0,00 |
| Family | MAX 9000 | MAX 9000 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 6,000 | 6,000 |
| Macrocells | 320 | — |
| Logic Array Blocks (LABs) | 20 | — |
| Maximum Operating Frequency | 144.9 MHz | — |
| Propagation Delay (tPD) | 10 ns (speed grade -10) | 15 ns |
| Versorgungsspannung | 4.5 V to 5.5 V | 5.0 V |
| Betriebstemperatur | -40 C to +85 C (industrial) | — |
| Gehäuse | 208-pin RQFP (S-PQFP-G208) | 208-pin RQFP (PowerQuad Flat Pack) |
| Montageart | Surface Mount | Surface Mount |
| Process Technology | CMOS EEPROM | — |
| Programmability | In-system (ISP) via IEEE 1149.1 JTAG | — |
| Global Dedicated Inputs | 16 | — |
| Architecture | Multiple Array MatriX (MAX) third-generation | — |
| RoHS-Status | unknown | [DATA_NEEDED: RoHS status] |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 320 |
| Flip-Flops | — | 484 |
| Configurable I/O Lines | — | 128 |
| Maximale Taktfrequenz | — | 117.6 MHz |
| I/O Voltage Compatibility | — | 3.3 V or 5 V |
| Configuration Technology | — | CMOS EEPROM (non-volatile) |
| In-System Programmability | — | Yes, via IEEE Std. 1149.1 JTAG |
| Terminal Pitch | — | 0.5 mm |
| Betriebstemperaturbereich | — | 0C to +70C (commercial) |
| Packaging | — | Tray |