EPM9320LC84-10 vs EPM9320ALI84-10N Vergleich
Detaillierter Direktvergleich von EPM9320LC84-10 von Intel und EPM9320ALI84-10N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM9320LC84-10 | EPM9320ALI84-10N |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $84,96 | $21,95 |
| Family | MAX 9000 EPLD | MAX 9000 |
| Device | EPM9320 | — |
| Macrocells | 320 | 320 |
| Usable Gates | 6000 (typical) | 6,000 to 12,000 |
| Logic Array Blocks (LABs) | 16 | 20 |
| Maximum User I/O Pins | 168 (varies by package) | — |
| Pin-to-Pin Logic Delay (tPD) | 10 ns | — |
| Maximum Frequency (fCNT) | [DATA_NEEDED: fCNT in MHz] | — |
| Supply Voltage (VCC) | 5.0 V (typical, see datasheet) | — |
| Process Technology | 0.7 µm CMOS EEPROM/UV-EPROM | CMOS EEPROM |
| Gehäuse | 84-pin PLCC (JEDEC MO-047) | 84-pin PLCC (J-lead, 1.270 mm pitch) |
| Montageart | Surface Mount (PLCC socket also common) | Surface Mount (PLCC socket compatible) |
| Betriebstemperatur | 0C to +70C (commercial) [DATA_NEEDED: exact grade suffix] | -40C to +85C (industrial) |
| Programming Interface | JTAG (IEEE 1149.1) boundary-scan, Altera ByteBlaster compatible | — |
| Configuration | Non-volatile EEPROM (instant-on, no boot PROM) | — |
| RoHS-Status | ROHS3 Compliant (per fpgalink listing) | — |
| Feuchtigkeitsempfindlichkeitsgrad (MSL) | MSL-3, 168 hours (per fpgalink listing) | — |
| Manufacturer Lead Time | 1-7 days (per fpgalink listing) | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Architecture | — | MAX (Multiple Array MatriX), 3rd generation |
| User I/O Pins | — | 56 |
| Pin-to-Pin Delay | — | 10 ns |
| Maximum Counter Frequency | — | 144.9 MHz |
| VCCINT (Core Supply) | — | 5.0 V |
| VCCIO (I/O Supply) | — | 3.3 V or 5.0 V |
| Input Logic Levels | — | TTL-compatible (at 5.0 V VCCINT) |
| In-System Programmability | — | Yes (IEEE Std. 1149.1 JTAG) |
| Configuration Memory | — | EEPROM, non-volatile |