EPM9320LC84-10 vs EPM9320LC84-15 Vergleich
Detaillierter Direktvergleich von EPM9320LC84-10 von Intel und EPM9320LC84-15 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM9320LC84-10 | EPM9320LC84-15 |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $84,96 | $17,95 |
| Family | MAX 9000 EPLD | MAX 9000 |
| Device | EPM9320 | — |
| Macrocells | 320 | 320 |
| Usable Gates | 6000 (typical) | 6,000 |
| Logic Array Blocks (LABs) | 16 | 20 |
| Maximum User I/O Pins | 168 (varies by package) | — |
| Pin-to-Pin Logic Delay (tPD) | 10 ns | — |
| Maximum Frequency (fCNT) | [DATA_NEEDED: fCNT in MHz] | — |
| Supply Voltage (VCC) | 5.0 V (typical, see datasheet) | 4.75 V to 5.25 V (5.0 V nominal) |
| Process Technology | 0.7 µm CMOS EEPROM/UV-EPROM | — |
| Gehäuse | 84-pin PLCC (JEDEC MO-047) | 84-pin PLCC (Plastic Leaded Chip Carrier) |
| Montageart | Surface Mount (PLCC socket also common) | Surface Mount |
| Betriebstemperatur | 0C to +70C (commercial) [DATA_NEEDED: exact grade suffix] | -40C to +85C (commercial) [DATA_NEEDED: exact grade] |
| Programming Interface | JTAG (IEEE 1149.1) boundary-scan, Altera ByteBlaster compatible | — |
| Configuration | Non-volatile EEPROM (instant-on, no boot PROM) | — |
| RoHS-Status | ROHS3 Compliant (per fpgalink listing) | [DATA_NEEDED: confirm from manufacturer] |
| Feuchtigkeitsempfindlichkeitsgrad (MSL) | MSL-3, 168 hours (per fpgalink listing) | — |
| Manufacturer Lead Time | 1-7 days (per fpgalink listing) | — |
| Series | — | EPM9320 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Propagation Delay (tPD) | — | 15 ns (max) |
| Maximale Taktfrequenz | — | 117.6 MHz |
| Programmability | — | 5.0 V in-system programmable (ISP) via JTAG |
| JTAG Interface | — | IEEE Std. 1149.1 boundary-scan compliant |
| Technology | — | CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX) |
| Built-in Pull-up Resistors | — | Yes, on every I/O pin |
| Architecture Feature | — | Pin-locking across design iterations |