EPM9320LC84-15 vs EPM9320ALC84-10 Vergleich
Detaillierter Direktvergleich von EPM9320LC84-15 von Intel und EPM9320ALC84-10 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM9320LC84-15 | EPM9320ALC84-10 |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $17,95 | $19,80 |
| Family | MAX 9000 | MAX 9000 |
| Series | EPM9320 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 320 | 320 |
| Usable Gates | 6,000 | — |
| Logic Array Blocks (LABs) | 20 | 16 |
| Propagation Delay (tPD) | 15 ns (max) | — |
| Maximale Taktfrequenz | 117.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5.0 V nominal) | — |
| Programmability | 5.0 V in-system programmable (ISP) via JTAG | — |
| JTAG Interface | IEEE Std. 1149.1 boundary-scan compliant | — |
| Gehäuse | 84-pin PLCC (Plastic Leaded Chip Carrier) | 84-pin PLCC (J-Lead) |
| Montageart | Surface Mount | Surface Mount / Through-Hole (PLCC socket) |
| Betriebstemperatur | -40C to +85C (commercial) [DATA_NEEDED: exact grade] | [DATA_NEEDED: commercial/industrial grade] |
| Technology | CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX) | CMOS EEPROM-based, third-generation MAX |
| Built-in Pull-up Resistors | Yes, on every I/O pin | — |
| Architecture Feature | Pin-locking across design iterations | — |
| RoHS-Status | [DATA_NEEDED: confirm from manufacturer] | [DATA_NEEDED] |
| Device | — | EPM9320 |
| Maximum User I/O Pins | — | 52 |
| Dedicated Inputs | — | 16 |
| Speed Grade | — | -10 (10 ns pin-to-pin delay) |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Supply Voltage (VCCINT) | — | 5.0 V |
| In-System Programmability | — | 5.0 V ISP via IEEE 1149.1 JTAG |
| PCI Compliance | — | PCI Local Bus Specification Rev. 2.2 (speed grade -10) |
| Non-Volatile Configuration | — | Yes (EEPROM cell, powers up in known state) |
| Architecture | — | MAX (Multiple Array MatriX) with FastTrack Interconnect |