EPM9320LC84-20 vs EPM9400LC84-20 Vergleich
Detaillierter Direktvergleich von EPM9320LC84-20 von Altera und EPM9400LC84-20 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM9320LC84-20 | EPM9400LC84-20 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,75 | $38,50 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 | 400 |
| User I/Os | 60 | — |
| Logic Family | CMOS (EEPROM-based) | — |
| Gehäuse | PLCC-84 (Plastic Leaded Chip Carrier) | 84-pin PLCC (Plastic Leaded Chip Carrier) |
| Pins | 84 | — |
| Propagation Delay (tPD) | 16 ns | — |
| Internal Counter Frequency | 118 MHz | — |
| Versorgungsspannung | 5.0 V | — |
| Betriebstemperatur | 0 C to 70 C | Commercial (0C to +70C) - assumed from -20 speed grade |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Dedicated Inputs | 4 (global clock / clear / OE) | — |
| Architecture | Multiple Array MatriX (MAX), 3rd generation | Multiple Array Matrix (MAX), 3rd generation, EEPROM-based |
| PCI Compliance | PCI Local Bus Specification Rev. 2.2 | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Usable Gates | — | 8,000 (6,000 to 12,000 typical range) |
| Flip-Flops | — | 580 |
| Maximum User I/O | — | 55 |
| Pin-to-Pin Propagation Delay | — | 20 ns (speed grade -20) |
| Maximum Counter Frequency | — | 144 MHz |
| Supply Voltage (VCCINT) | — | 5 V |
| I/O Voltage (VCCIO) | — | 3.3 V or 5 V (configurable) |
| In-System Programming | — | Yes (IEEE 1149.1 JTAG) |
| Process Technology | — | CMOS EEPROM |
| Montageart | — | Surface Mount (PLCC socket or SMT land pattern) |