EPM9320LC84-20N vs EPM9320LI84-20N Vergleich
Detaillierter Direktvergleich von EPM9320LC84-20N von Intel und EPM9320LI84-20N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM9320LC84-20N | EPM9320LI84-20N |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $10,25 | $9,75 |
| Series | MAX 9000 | — |
| Logic Family | CMOS (EEPROM-based) | CMOS, EEPROM-based |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 6,000 | 6,000 to 12,000 |
| Macrocells | 320 | 320 |
| User I/Os | 60 | — |
| Anzahl der Pins | 84 | — |
| Package Type | Plastic Leaded Chip Carrier (PLCC-84, J-bend) | — |
| Package Code | QCCJ | — |
| Propagation Delay (tPD) | 16 ns | 20 ns (speed grade -20) |
| Internal Frequency | 118 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| Betriebstemperatur | 0 C to +70 C (Commercial) | 0 C to +70 C (commercial) |
| Programming | 5.0-V In-System Programmable via JTAG (IEEE 1149.1) | — |
| Montageart | Surface Mount (J-bend) | — |
| Terminal Form | J BEND | — |
| MSL-Level | [DATA_NEEDED: MSL moisture sensitivity level] | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance status] |
| Family | — | MAX 9000 |
| User I/O Pins | — | 60 |
| Total Pins | — | 84 |
| Gehäuse | — | PLCC-84 (Plastic Leaded Chip Carrier, J-lead) |
| Pin-to-Pin Delay | — | 16 ns (per DigChip spec block) |
| Maximum Counter Frequency | — | 118 MHz |
| Versorgungsspannung | — | 5.0 V |
| Programming Interface | — | IEEE 1149.1 JTAG, in-system programmable |
| Architecture | — | Multiple Array MatriX (MAX) - third generation |
| Process Technology | — | Advanced CMOS EEPROM |