EPM9320RC208-20N vs EPM9320RC208-10 Vergleich
Detaillierter Direktvergleich von EPM9320RC208-20N von Altera und EPM9320RC208-10 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM9320RC208-20N | EPM9320RC208-10 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $0,00 | $26,40 |
| Device Family | MAX 9000 | — |
| Logic Type | Complex Programmable Logic Device (CPLD) | — |
| Usable Gates | 6,000 | 6,000 |
| Macro Cells | 320 | — |
| Logic Array Blocks | 20 | — |
| Maximum Pin-to-Pin Delay (tPD) | 20 ns | — |
| Maximum Operating Frequency | 100 MHz | — |
| Versorgungsspannung | 5.0 V | 5 V |
| Configuration Memory | EEPROM (non-volatile) | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | — |
| User I/O Pins | 168 | — |
| Gehäuse | 208-pin RQFP (PowerQuad II) | 208-pin RQFP (RC) |
| Montageart | Surface Mount | — |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | Commercial (0C to +70C) - 'C' suffix |
| RoHS-Status | [DATA_NEEDED: RoHS status] | ROHS3 Compliant (per fpgalink listing) |
| Lead Finish | [DATA_NEEDED: lead finish] | — |
| MSL-Level | [DATA_NEEDED: MSL level] | — |
| Family | — | MAX 9000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 320 |
| Logic Array Blocks (LABs) | — | [DATA_NEEDED: LAB count] |
| Speed Grade | — | -10 |
| Programming Interface | — | JTAG (ByteBlaster/BitBlaster) |
| Non-volatile Configuration | — | Yes (EPROM/EEPROM based) |
| Design Tool Support | — | MAX+PLUS II, Quartus (legacy) |
| Feuchtigkeitsempfindlichkeitsgrad (MSL) | — | 3 (168 Hours) |
| Lead Time | — | 1-7 days (per fpgalink listing) |