EPM9320RI208-20N vs EPM9320RI208-20 Vergleich

Detaillierter Direktvergleich von EPM9320RI208-20N von Altera und EPM9320RI208-20 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM9320RI208-20N EPM9320RI208-20
Marke Altera Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus NRND Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $0,00 $18,95
Device Family MAX 9000 (EPM9320) —
Logic Type EEPROM-based Complex Programmable Logic Device (CPLD) —
Macrocells 320 320
Flip-Flops 484 —
Propagation Delay (tPD) 20 ns 20 ns
Supply Voltage (VCC) 5.0 V 5.0 V
I/O Voltage Tolerance 3.3 V or 5 V configurable —
Gehäuse 208-pin PQFP (Plastic Quad Flat Pack) 208-pin RQFP (Power Quad Flat Pack)
Package Lead Pitch 0.500 mm —
Number of Terminals 208 —
Betriebstemperaturbereich -40C to +85C (Industrial) —
In-System Programmability Yes, 5.0 V ISP via JTAG Yes - IEEE 1149.1 JTAG, 5.0-V ISP
JTAG Interface IEEE Std. 1149.1 compliant —
Configuration Memory EEPROM (non-volatile) —
Dedicated Input Pins 4 (low-skew global distribution) 4 (low-skew global)
Minimum DC Input on I/O Pins -0.5 V —
Minimum DC Input on Dedicated Inputs -0.3 V —
Input Undershoot/ Overshoot -2.0 V / 7.0 V for <20 ns (no-load) —
Montageart Surface Mount Surface Mount
RoHS-Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance]
Family — MAX 9000
Device Type — CPLD (Complex Programmable Logic Device)
Usable Gates — 6,000
Maximum Operating Frequency — 100 MHz
Logic Elements / LABs — 20 Logic Array Blocks (16 macro cells each)
Programmable Interconnect — Programmable Interconnect Array (PIA)
User I/O Pins — [DATA_NEEDED: I/O pin count for 208-pin RQFP]
Operating Temperature Grade — Industrial
Technology — CMOS EEPROM
MSL-Level — [DATA_NEEDED: MSL rating]

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